FPGA Verification Engineer

Company Description

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges.

At Arista we value the diversity of thought and perspectives that each employee brings to the table. We  believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.

Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.

Job Description

What You’ll Do

We are looking for a motivated individual to join our FPGA Design Team at our headquarters in Santa Clara, CA, in the heart of Silicon Valley. In this position, you will be responsible for designing test bench, simulating, and testing FPGA RTL code that forms the backbone of our next generation systems.

• Create and maintain test benches in Verilog/SystemVerilog
• Create BFM, RTL models for new and existing designs
• Develop the verification test plans and test cases
• Review the design functional coverage

Concepts and Skills: 

• Work with Data and control architectures of a modern ethernet switch, including chip IO interfaces such as Interlaken, Ethernet PHY/MAC, PCIe, SMBus, SPI, MDIO, JTAG, etc.
• Work with Protocols using Ethernet, such as PTP, SFlow, POE, etc.
• Work with Simulation software for FPGA functional verification

Qualifications

• 2-4 years of designing Verilog/SystemVerilog RTL code
• Proficient in design verification tools and languages (SystemVerilog, SVA, Modelsim, Perl, Python, Unix shell scripts)
• Experience in the chip level verification environment setups, code/functional coverage collection
• Motivated, passionate, with sense of urgency and commitment to achieve the targeted goals
• Strong scripting, debugging and problem solving skills
• Excellent in-person, video, and written communication skills

Compensation Information:

The new hire base pay for this role has a salary range of $130,000 to $180,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

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Additional Information

Arista Networks is an equal opportunity employer.  Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law.  All your information will be kept confidential according to EEO guidelines.